1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and more particularly, to a semiconductor memory device including a redundancy memory cell remedying a defective memory cell when a defect occurs in an ordinary memory cell array.
2. Description of the Background Art
In a semiconductor memory device in general, in terms of production yield, a redundancy memory cell is provided in a memory cell array in order to remedy a defective bit, and a memory cell in which a defect occurs is replaced with the redundancy memory cell.
Description will now be given of a conventional semiconductor memory device with reference to the drawings. FIG. 12 is a block diagram showing a configuration of the conventional semiconductor memory device.
In FIG. 12, the semiconductor memory device includes a row decoder 101, a memory cell array 102, a shift redundancy circuit 103, a shift redundancy control circuit 104, a sense amplifier portion 105, a multiplexer 106, and a burst counter 107. Memory cell array 102 includes bit lines BL, /BL ("/" indicates a complementary signal line or an inverted signal hereinafter), word lines WL, memory cells MC, redundancy bit lines BR, /BR, and redundancy memory cells MR.
An ordinary memory cell array is configured of a plurality of memory cells MC each holding one-bit information. Redundancy memory cell MR has the same configuration as that of memory cell MC, and holds one-bit information. A plurality of redundancy memory cells MR arranged in the column direction configure a redundancy memory cell array. The redundancy memory cell replaces a defective portion when a defect occurs in an ordinary memory cell array configured of memory cells MC.
Memory cells MC are connected to bit lines BL, /BL in the column direction. Similarly, redundancy memory cells MR are connected to redundancy bit lines BR, /BR in the column direction. Memory cells MC and redundancy memory cells MR are connected to word lines WL.
An address signal X is applied to row decoder 101. Row decoder 101 decodes the applied address signal X, and brings a predetermined word line WL to a selected state.
Shift redundancy circuit 103 is a switching circuit disconnecting, when a defect occurs in ordinary memory cell MC, a column including the defect from sense amplifier portion 105 and connecting an adjacent column thereto. The operation of shift redundancy circuit 103 is controlled by shift redundancy control circuit 104.
Data provided from shift redundancy circuit 103 is applied to sense amplifier portion 105. The data is provided to multiplexer 106 after being amplified to a predetermined amplitude.
Multiplexer 106 selects a plurality of data provided from sense amplifier portion 105 in response to multiplexer control signals provided from burst counter 107, and provides one of the data. A predetermined clock signal CLK is applied to burst counter 107. Burst counter 107 provides multiplexer control signals in synchronism with clock signal CLK. A binary counter, for example, is used as the burst counter.
According to the above operation, when a defect occurs in memory cell MC, data in the defective memory cell is replaced with data of redundancy memory cell MR, and data read out from the memory cell array simultaneously can be provided sequentially in synchronism with clock signal CLK.
The configuration of the shift redundancy circuit and sense amplifier portion shown in FIG. 12 will now be described with reference to FIG. 13.
In FIG. 13, the shift redundancy circuit and sense amplifier portion includes a bit line precharge circuit 111, a shift redundancy circuit 112, a writing circuit 113, and a sense amplifier 114.
Bit line precharge circuit 111 includes NMOS transistors Q201, Q202, and a PMOS transistor Q203. Bit line precharge circuit 111 precharges bit lines BL, /BL to a predetermined voltage level.
Shift redundancy circuit 112 includes resistances R201, R202, NMOS transistors Q211 to Q214, PMOS transistors Q216 to Q219, and fuse elements F201, F202. Shift redundancy circuit 112 switches connection between bit lines BLi /BLi and signal lines BA, /BA connected to sense amplifier 114 by disconnecting fuse elements F201, F202. More specifically, shift redundancy circuit 112 replaces a memory cell including a defect with a redundancy memory cell to remedy a defective bit by switching connection between bit lines BL, /BL and signal lines BA, /BA from sense amplifier 114.
Writing circuit 113 includes NMOS transistors Q221 to Q224, and NOR gates G201 to G204. Writing circuit 113 transmits an externally applied data signal to memory cell MC through shift redundancy circuit 112 and bit lines BL, /BL, and writes predetermined data in a predetermined memory cell.
Sense amplifier 114 includes transistors Q231 to Q238, PMOS transistors Q241, Q242, NMOS transistors Q243 to Q248, resistances R203, R204, and an inverter G211. Sense amplifier 114 amplifies a data signal applied through shift redundancy circuit 112 to a predetermined amplitude for output.
In the above conventional semiconductor memory device, since a memory cell including a defect is replaced with a redundancy memory cell by shift redundancy circuit 112, a shift redundancy circuit which is a switching circuit is connected in series in a path from input of an address signal X to output of output data Dout, thereby increasing an access time.